1. Field of the Invention
This disclosure relates generally to non-volatile memory devices and methods of manufacturing the same. More particularly, this disclosure relates to a non-volatile memory device having a fin body and methods of manufacturing the device.
2. Description of the Related Art
Generally, semiconductor devices are classified into volatile memory devices and non-volatile memory devices. An example of a volatile memory device includes a dynamic random access memory (DRAM) device. Examples of non-volatile memory devices include a read only memory (ROM) device, an electrically erasable programmable read only memory (EEPROM) device, etc. An example of an EEPROM device includes a flash memory device.
A conventional planar flash memory device includes source/drain regions and a channel region formed on a semiconductor substrate such as a silicon wafer, a first dielectric layer formed on the semiconductor substrate, a floating gate electrode formed on the first dielectric layer, a second dielectric layer formed on the floating gate electrode, and a control gate electrode formed on the second dielectric layer.
Recently, as flash memory devices have been highly integrated, a flash memory device having a fin body in which an active region is formed has been widely developed. Examples of fin-type flash memory devices are disclosed in U.S. patent application Publication Nos. 2003-151077, 2003-178670 and 2003-42531.
On the other hand, the operation voltage of the flash memory device may be determined in accordance with a first capacitance C1 between the channel region and the floating gate electrode, and a second capacitance C2 between the floating gate electrode and the control gate electrode. The coupling ratio Cr of the flash memory device is the ratio between the operation voltage Vg applied to the control gate electrode and the voltage Vf induced in the floating gate electrode. The coupling ratio may be represented by the following formula:Cr=Vf/Vg=C2/(C1+C2)
Since the first dielectric layer in the fin-type flash memory device is formed on an upper surface and side surfaces of the fin body that is protruded from the semiconductor substrate, the first dielectric layer in the fin-type flash memory device has an area broader than that of the first dielectric layer in the planar flash memory device. Thus, the first capacitance between the channel region formed in the fin body and the floating gate electrode is increased so that the coupling ratio is decreased. This may cause an increase in the operation voltage of the fin-type flash memory device.
Further, because the floating gate electrode in the fin-type flash memory device encloses the first dielectric layer on the fin body, a process align margin between the floating gate electrode and the fin body may not be sufficiently guaranteed.